glibc-2.6.1 test errors
Athena
lists at vega.uk.net
Fri Oct 5 14:14:31 MDT 2007
On Friday 05 October 2007 17:31:56 Alexander E. Patrakov wrote:
> Jeremy Huntwork wrote:
> > On Fri, 5 Oct 2007 07:25:48 -0600, Jeremy Huntwork
<jhuntwork at linuxfromscratch.org> wrote:
> >> grep Error /mnt/lfs/jhalfs/test-logs/065-glibc
> >> make[3]: [/sources/glibc-build/posix/annexc.out] Error 1 (ignored)
> >>
> >> I'll be running a test on trunk now just to make sure that everything is
> >> kosher.
> >
> > The development book is fine. It looks like those optimizations are
> > causing you problems.
>
> It is known that on different Intel CPUs, glibc chooses at runtime
> different algorithms for certain floating-point operations (grep for
> HWCAP_I386_XMM, for example, which corresponds to SSE support). So here
> it may well be that this part of the Glibc testsuite in fact a testsuite
> for the CPU. For the meaningful comparison of the results, I ask both
> you and the original poster to post the contents of /proc/cpuinfo.
>
> --
> Alexander E. Patrakov
On Friday 05 October 2007 17:31:56 Alexander E. Patrakov wrote:
> Jeremy Huntwork wrote:
> > On Fri, 5 Oct 2007 07:25:48 -0600, Jeremy Huntwork
<jhuntwork at linuxfromscratch.org> wrote:
> >> grep Error /mnt/lfs/jhalfs/test-logs/065-glibc
> >> make[3]: [/sources/glibc-build/posix/annexc.out] Error 1 (ignored)
> >>
> >> I'll be running a test on trunk now just to make sure that everything is
> >> kosher.
> >
> > The development book is fine. It looks like those optimizations are
> > causing you problems.
>
> It is known that on different Intel CPUs, glibc chooses at runtime
> different algorithms for certain floating-point operations (grep for
> HWCAP_I386_XMM, for example, which corresponds to SSE support). So here
> it may well be that this part of the Glibc testsuite in fact a testsuite
> for the CPU. For the meaningful comparison of the results, I ask both
> you and the original poster to post the contents of /proc/cpuinfo.
>
> --
> Alexander E. Patrakov
Hello
As requested my /proc/cpuinfo is attached.
(Sorry not sure if you guys perfer stuff like this attached or pasted into the
email body)
Jeremy: I didn't deviate from chapter 5 at all and the glibc test results
which i posted were with the default optimization. Strangely dropping the
optimization back to default seems to increase the math error.
PS: My apologies in advance if this email arrives twice - for some bizarre
reason my server (postfix) seemed to throw a wobbler with LFS greylisting!
Many Thanks
Athena
-------------- next part --------------
processor : 0
vendor_id : GenuineIntel
cpu family : 15
model : 4
model name : Intel(R) Pentium(R) 4 CPU 3.20GHz
stepping : 1
cpu MHz : 3264.781
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc pni monitor ds_cpl cid xtpr
bogomips : 6531.45
clflush size : 64
processor : 1
vendor_id : GenuineIntel
cpu family : 15
model : 4
model name : Intel(R) Pentium(R) 4 CPU 3.20GHz
stepping : 1
cpu MHz : 3264.781
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc pni monitor ds_cpl cid xtpr
bogomips : 6528.18
clflush size : 64
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